The present invention relates to an apparatus and method for testing devices-under-test, for example, semiconductor integrated circuits such as an LSI wafer, and more particularly relates to a test apparatus and a test method capable of simultaneously performing independent tests on a large number of devices-under-test.
Conventionally, independent tests are simultaneously carried out on a plurality of devices-under-test (for example, Japanese Utility Model Application Laid-Open No. 64-47148/1989). FIG. 1 is a block diagram of a conventional test apparatus disclosed in Japanese Utility Model Application Laid-Open No. 64-47148/1989. This test apparatus comprises: a plurality of test units 31–33 controlled by microprocessors storing test programs which are operated separately; a processor unit 1 having a monitor function for monitoring the operating conditions of the respective test units 31–33 and a man-machine interface function; and an interface control unit 2 for controlling the communication routes between the respective test units 31–33 and the processor unit 1. The test units 31–33 and devices-under-test 41–43 are connected one to one. The test units 31–33 have the same internal structure, and comprise microprocessors 51–53 for controlling the internal operations, test circuits 61–63 for testing the corresponding devices-under-test 41–43, and interfaces 71–73 for communicating with the interface control unit 2.
When testing a plurality of devices-under-test by such a structure, first, the processor unit 1 outputs a communication request to the test unit 31 through the interface control unit 2. After the interface control unit 2 recognizes the communication request, it ensures a communication route to the test unit 31 and transmits the communication request from the processor unit 1 to the microprocessor 51 through the interface 71 in the test unit 31. The microprocessor 51 sends back a notice to the processor unit 1 through the interface 71 and the interface control unit 2 according to the situation. More specifically, if communication is feasible, the microprocessor 51 sends back a notice indicating that communication is feasible, and, if communication is infeasible, the microprocessor 51 sends back a notice indicating that communication is infeasible.
If the notice sent from the microprocessor 51 indicates that communication is feasible, the processor unit 1 transmits a request to start a test to the microprocessor 51 through the interface control unit 2 and the interface 71. After the microprocessor 51 recognizes the request to start a test, it executes the test program and operates the test circuit 61 to start testing the device-under-test 41. Similarly, the processor unit 1 performs this operation on the test units 32 and 33 one after another and starts the tests of the devices-under-test 42 and 43. Moreover, the processor unit 1 can respond to the requests from the respective test units 31–33 by polling the operating conditions of the test units 31–33 through the interface control unit 2.
When transferring data indicating completion of test from the test unit 31, first, the microprocessor 51 sends a transfer request to the interface control unit 2 through the interface 71 in the test unit 31. After the interface control unit 2 recognizes the transfer request, it outputs the transfer request to the processor unit 1 and ensures a communication route between the processor unit 1 and the microprocessor 51. When the processor unit 1 recognizes the transfer request from the microprocessor 51 by polling, it sends back a notice indicating that data transfer is feasible to the microprocessor 51 through the interface control unit 2 and the interface 71. The microprocessor 51 recognizes that data transfer is feasible, and transfers data indicting completion of the test to the processor unit 1.
Thereafter, the processor unit 1 opens the communication route between the processor unit 1 and the microprocessor 51 in the interface control unit 2 and processes the data sent from the microprocessor 51, and then monitors whether or not there is a transfer request of data indicating completion of test from other test units 32 or 33 by polling. The processor unit 1 repeats this operation, and the tests are completed when data indicating completion of test is transferred from all the test units 31–33.
Besides, in the case where test results including measurement data are transferred to the processor unit 1 from the respective test units 31–33, similarly to the transfer of data indicating completion of test, the processor unit 1 communicates with the microprocessors 51–53 one after another, the respective microprocessors 51–53 transfer the test results, and the sent data is processed in the processor unit 1.
In recent years, in order to improve the efficiency of testing a plurality of devices-under-test, a wafer batch test has started to be used. In the case where independent tests are simultaneously performed on a large number of devices-under-test by the above-mentioned structure and test method of the conventional technique as in the wafer batch test, since test units are connected one to one to the respective devices-under-test, the same number of test units and microprocessors in the test units as the number of devices-under-test to be tested simultaneously are provided, and it is necessary to output test start requests from one processor unit by sequentially communicating with a large number of microprocessors in the respective test units one by one through the interface control unit. Moreover, one processor unit needs to respond to all the transfer requests of data indicating completion of test and the transfer requests of test results from a large number of microprocessors.
In other words, since one processor unit needs to perform control of all the microprocessors (requests to start a test, etc.) and management (such as test completion requests from the respective microprocessors, transfer requests of test results, and processing of the transferred test results), the communication time between the processor unit and each microprocessor and the processing time in the processor unit increase with an increase in the number of devices-under-test to be tested simultaneously. Furthermore, the transfer time of test results obtained in the respective test units and the waiting time until the test results are transferred increase due to the influence of an increase in the communication time and the processing time. As a result, there is the problem of lowered testing efficiency which influences mass-production.